From February 18 to 22, the IEEE Solid State Circuit conference will take place in San Francisco. Leading chip developers, including Intel, Marvell, and Synopsys, will update the industry about their latest memory interface developments. Each company is set to showcase circuit designs for 3-nm processes with speeds of up to 224 Gbps.
Memory standard DDR6 specifications are expected to be ratified in 2024. Data transmission speeds will likely range between 12.8 Gbps and 17 Gbps per contact on the data bus. To accommodate this, updated protocols and new circuit designs are necessitated. The announcements due in February attest to the preparations Intel, Marvell, and Synopsys are making for the launch of DDR6 and future memory versions.
Intel’s presentation will delve into the organization of the physical layer (PHY) of the memory signal interface, which is analog by design. The challenge is to minimize noise levels and synchronize signals optimally — factors that depend on transistor properties and the fabrication process of the controllers. Reportedly, Intel has adapted DAC circuitry for 3-nm FinFET transistors. The power consumption level is estimated at 3 pJ/bit, a marker of efficiency given the need to moderate consumption, even when the bandwidth increases.
In response, Synopsys will present a licensable circuit design for a transmitter/receiver sporting similar characteristics. Synopsys’ solution will offer a maximum interface speed of 224 Gbps at the same power consumption rate of 3 pJ/bit. The design is penciled in for 3-nm class FinFET procedures — a specification that subtly excludes Samsung, who is transitioning towards Gate All Around FET (GAAFET) transistors in its 3-nm production.
Not to be outdone, the memory controller and signal processor developer, Marvell, will also lay out its blueprint for high-speed future memory. Marvell’s digital controller will process and transmit signals at a capacity of up to 212 Gbps for 5-nm FinFET processes. The notable leeway in performance speed should facilitate future memory speed build-up beyond what is expected for the DDR6 standard. This will prove critical for AI and machine learning applications.
